Digital filters are being used in an increasing number of electronic devices. One commonly used type of digital filter is a finite impulse response (FIR) filter. The FIR filter is a sampled data filter characterized by its impulse response. Its input signal is a discrete time sequence which may be analog or digital while its output is also a discrete time sequence which is the convolution of the input sequence and the filter impulse response. The relationship between the input samples Vi[n] and output samples Vo[n] is given by:Vo[n]=A0Vi[n]+A1Vi[n−1]+A2Vi[n−2]+ . . . +AN−1Vi[n−N+1]  (1)Applying the Z-transform, the previous relationship can be represented as:Vo(z)=A0Vi(z)+A1Vi(z)Z−1+A2Vi(z)Z−2+ . . . +AN−1Vi(z)Z−(N−1)  (2)The components of the coefficient vector A0 . . . AN−1 are ordinarily referred to as filter tap weights. In the impulse response of the filter, there is no feedback and thus it is an all zero filter, which means that the response is shaped by placement of transmission zeroes in the frequency domain. This class of filters facilitates the implementation of adaptive filter structures.
FIR filters may be implemented in the analog domain or in the digital domain. An analog FIR filter implementation typically performs multiplication of the tap weights and the input signal samples using analog multipliers, and sums each term using an analog summer. In a digital FIR filter implementation, multiplication of the tap weights and the input signal samples as well as summation of each term in equation 1, are typically performed digitally.
Although digital FIR filters normally produce an output signal with a higher signal to noise ratio than an analog FIR filter, digital FIR filters are impractical for some applications. For example, analog FIR filters may normally operate at much higher speeds and lower power consumption than digital FIR filters. Analog FIR filters, therefore, are most commonly used in high speed applications such as, for example, magnetic disk drive read channels, radios, modems, and communication channels. However, existing architectures for FIR filters have various drawbacks when used for analog FIR filters.
One existing analog FIR implementation is an analog delay line based architecture. This architecture typically includes an analog delay line, analog multipliers, and an N-input analog summing block. The filter output is the sum of the inner product of the input vector and the coefficient vector. The analog delay line is normally composed of a chain of analog sample and hold amplifiers. Each sample and hold amplifier samples during the holding time of the preceding sample and hold amplifier in the chain. The problem with the delay line based architecture is that in the process of sampling, the signal acquires a certain amount of noise, offset, and distortion. After the analog signal has passed through a chain of sample and hold amplifiers, the level of distortion is often unacceptable.
An analog FIR filter architecture that avoids multiple sampling of the input signal is one employing round robin sampling of the input signal. In this type of architecture, the signal is sampled in a round robin manner, preventing error accumulation from one sample and hold amplifier to the next. Each sample and hold amplifier's output connects to an analog multiplier. In order to simulate delay, the output of the sample and hold amplifier is multiplied in the analog multiplier by a series of tap weights that are shuffled every clock cycle. For example, in a three tap filter, the output of a given sample and hold amplifier will be multiplied by tap weight A0 during the first clock cycle after sampling, by tap weight A1 during the second clock cycle after sampling, and by tap weight A3 on the third clock cycle after sampling.
The problem with this architecture is that the digital tap weights need to be shuffled every clock cycle. A large number of signals, therefore, need to be switched on every clock cycle. For example, in a 9 tap filter using 6-bit digital-to-analog converters, 54 signals are switched during every clock cycle. This heavy switching consumes a large amount of power, especially if the signals are at full CMOS levels. In addition, switching noise can be significant and can affect filter performance. For certain digital-to-analog converter (DAC) circuit implementations where overlapping clocks are required, both true and complement signals are needed. This will double the number of shuffled signals, increasing both power consumption and digital noise generation. Moreover, the shuffling of coefficients every clock cycle poses a great demand on the settling time of the DACs. Lesser settling time is attained at the expense of larger power consumption as faster DAC's consume more power.
The previous two analog FIR filter structures described above are known as direct form FIR filter implementations. In an alternative filter implementation the input signal is multiplied by all of the tap coefficients, and delayed versions of the taps are combined together at the output to form the final filter output. Integrators integrate the final filter output over N-clock cycles for an N-tap filter. During each clock cycle, a new multiplying DAC is switched and accumulated in a round robin manner on the integrating capacitor of the integrator block. This FIR filter architecture thus eliminates tap coefficient shuffling at the input of each multiplying DAC.
The problem with this architecture, however, is in the circuit implementation of the integrators and multiplying DACs. In order to achieve high speed and low power consumption, a current-based multiplying DAC is normally used. Then, to perform summation, the current produced by the multiplying DACs is switched onto the capacitor which sums up the charge over N clock cycles. Although such circuit implementation may achieve greater speed, filter performance is greatly diminished due to both clock jitter and integration of switching transients.
The first and second architectures described above employ multiple sample and hold circuits. Ideally, each sample and hold circuit would hold its output at a precise time during a clock transition. Precisely defined sampling instants, however, are difficult to achieve in actual sample and hold circuit implementations. Often, when multiple sample and hold circuits are used in a larger circuit, each sample and hold samples at a slightly different time. In other words, the actual sampling time can occur within a certain neighborhood of a clock edge and the precise sampling time will often vary among multiple sample and holds.
Sample and hold circuit timing errors can lead to several problems. First, the signal to noise ratio of the output of the FIR filter may be disturbed. The equations used to derive a FIR filter assume that an input signal is being sampled at precise instants. When sample and hold circuit timing errors cause the sampling time to deviate from those precisely defined instants, the signal is being sampled at the wrong time and, typically, the signal will have changed value since the precisely defined sampling instant. In effect, the FIR filter receives an incorrect signal value because it samples the signal at an improper time.
In addition, sample and hold timing errors may cause clock jitter as the output of a FIR filter is often fed back into a phase locked loop to generate the clock used to control sampling. Clock jitter on the FIR filter clock further degrades filter performance.
One approach for a high speed FIR filter architecture with precise timing acquisition consumes less power than existing architectures and eases circuit implementation of FIR filters as is disclosed in U.S. Pat. No. 6,032,171, which is incorporated by reference herein. In this type of implementation an input signal is coupled to a master input of a “master” sample and hold circuit. A plurality of “slave” sample and hold circuits are coupled to the output of the master sample and hold circuit. The outputs of these circuits may then be used in the taps of a FIR filter by multiplexing the outputs to a plurality of multipliers in a round robin manner.
This FIR filter architecture implementation, however, can lead to several problems. First, round robin digital logic consumes more power. In addition, use of a large number of taps increases parasitic capacitance at the output. Accordingly, the resistive load at the output and the parasitic capacitance form a dominant pole which results in degradation of the filter's speed. One approach of correcting this problem includes cascading the filter with a cascode transistor to decouple the parasitic capacitance from the output node where the signal is actually observed. Since, however, the power supply is limited, typically 5 volts, headroom problems arise. Another disadvanage which exists is that the FIR output gain is limited by total output common-mode voltage.
Accordingly, a need has arisen for a high speed FIR filter architecture that eliminates the need for round robin digital logic and enables the use of a large number of taps without speed degradation. Moreover, there is a need for a high speed FIR filter architecture that is not limited by the total output common-mode voltage.